1. Field of the Invention
The present invention relates to a method of manufacturing a wiring substrate and, more particularly, a method of manufacturing a wiring substrate, which is applicable to a substrate of a semiconductor package.
2. Description of the Related Art
In the prior art, there is the build-up wiring substrate equipped with a multilayer wiring in which wiring layers and resin layers are formed alternately on a substrate. In the method of manufacturing such build-up wiring substrate, first, a wiring layer made of copper is formed on the substrate. Then, unevenness is formed by etching a surface of the wiring layer by about 1 to 2 μm. Then, an interlayer insulating layer is formed by pasting a resin film on the wiring layer, or the like.
By forming unevenness (concave-convex) to a surface of the wiring layer to roughen, adhesion between the wiring layer and the overlying interlayer insulating layer can be secured. Also, the step of forming a via hole reaching the wiring layer in the interlayer insulating layer and the step of forming an overlying wiring layer connected to the wiring layer via the via hole are repeated, and thus a desired multilayer can be obtained.
As the technology related with the above prior art, in Patent Literature 1 (Patent Application Publication (KOKAI) 2003-8199), it is set forth that uneven portions are formed on a surface of a copper layer by the etching using a sulfuric acid hydrogen peroxide mixture, and then the surface of the copper layer is roughened by applying the blackening process to the uneven portions.
Also, in Patent Literature 2 (Patent Application Publication (KOKAI) Hei-2-238942), it is set forth that, in order to improve adhesion between a copper foil and a resin, a coating film made of copper oxide is formed on a surface of the copper foil, and then the surface of the copper foil is roughened by fusing/removing the copper oxide by means of the chemical process using acid.
As described above, in the method of manufacturing the build-up wiring substrate in the prior art, the surface of the wiring layer is etched by about 1 to 2 μm in order to secure the adhesion between the wiring layer and the overlying interlayer insulating layer (resin).
However, as shown in FIGS. 1A and 1B, when the wiring layers 200 are made minute (line:space=10:10 μm or less), a ratio of an etching amount to a line width of a wiring layer 200 (FIG. 1A) before the roughening process is increased. Therefore, the wiring layer 200 (FIG. 1B) after the roughening process is considerably narrowed and goes out of a design specification, and furthermore the pattern jump (pattern disappearance) is caused. Also, when a line width of the wiring layer 200 becomes narrower than the design specification, the problem of a delay of the electric signal arises. As a result, such wiring substrate cannot easily respond to the wiring substrate of the high-performance semiconductor chip.
Conversely, when an etching amount is reduced in order to ease the thinning of the wiring layer 200, the unevenness is made small. Therefore, satisfactory adhesion between the wiring layer 200 and the interlayer insulating layer (resin) cannot be obtained, and thus reliability of the wiring substrate is decreased.